View IDTCSPT855_306462.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

IDTCSPT855 2.5V PLL CLOCK DRIVER
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
2.5V PHASE LOCKED LOOP CLOCK DRIVER
IDTCSPT855 PRELIMINARY
* PLL clock driver for DDR (Double Data Rate) synchronous DRAM applications * Spread spectrum clock compatible * Operating frequency: 60MHz to 180MHz * Low jitter (cycle-to-cycle): 50ps * Distributes one differential clock input to four differential clock outputs * Enters low power mode and 3-state outputs when input CLK signal is less than 20MHz or PWRDWN is low * Operates from dual 2.5V supplies * Consumes <200A quiescent current * External feedback pins (FBIN, FBIN) are used to synchronize outputs to input clocks * Available in TSSOP package
FEATURES:
DESCRIPTION:
The CSPT855 is a high-performance, low-skew, low-jitter zero delay buffer that distributes one differential clock input pair(CLK, CLK ) to four differential output pairs (Y [0:3], Y [0:3]) and one differential pair of feedback clock outputs (FBOUT, FBOUT). When PWRDWN is high, the outputs switch in phase and frequency with CLK. When PWRDWN is low, all outputs are disabled to a highimpedance state (3-state), and the PLL is shut down (low-power mode). The device also enters this low-power mode when the input frequency falls below a suggested detection frequency that is below 20MHz (typical 10MHz). An input frequency detection circuit detects the low-frequency condition, and after applying a >20MHz input signal, this detection circuit reactivates the PLL and enables the outputs. When AVDD is tied to GND, the PLL is turned off and bypassed for test purposes. The CSPT855 is also able to track spread spectrum clocking for reducted EMI. Since the CSPT855 is based on PLL circuitry, it requires a stabilization time to achieve phase-lock of the PLL. This stabilization time is required following power up.
FUNCTIONAL BLOCK DIAGRAM
3
Y0
2 12
Y0 Y1 Y1 Y2 Y2
PWRDWN AVDD
24
9
POWERDOWN AND TEST LOGIC
13 17 16 26
Y3
27
Y3 FBOUT FBOUT
CLK CLK FBIN FBIN
6 7
19
PLL
23 22
20
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
1
c 2003 Integrated Device Technology, Inc.
APRIL 2003
DSC-6203/3
IDTCSPT855 2.5V PLL CLOCK DRIVER
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
PIN CONFIGURATION
1 2 3 4 5 6 7 8 9 10 11 12 13 14
ABSOLUTE MAXIMUM RATINGS(1)
Symbol VDDQ, AVDD Rating Supply Voltage Range Input Voltage Range Output Voltage Range Input Clamp Current Output Clamp Current Max -0.5 to +3.6 -0.5 to VDDQ + 0.5 -0.5 to VDDQ + 0.5 50 50 50 100 105.8 - 65 to +150 Unit V V V mA mA mA mA C/W C VI(2) VO(2) IIK (VI < 0 or VI < VDDQ) IOK (VO < 0 or VO > VDDQ)
GND Y0 Y0 VDDQ GND CLK CLK VDDQ AVDD AGND VDDQ Y1 Y1 GND
28 27 26 25 24 23 22 21 20 19 18 17 16 15
GND Y3 Y3 VDDQ PWRDWN FBIN FBIN VDDQ FBOUT FBOUT VDDQ Y2 Y2 GND
Continuous Output Current IO (VO = 0 to VDDQ) VDDQ or GND JA(3) TSTG Continuous Current Package Thermal Impedance Storage Temperature Range
NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed. This value is limited to 3.6V maximum. 3. The package thermal impedance is calculated in accordance with JESD 51.
TSSOP TOP VIEW
PIN DESCRIPTION
Pin Name AGND AVDD CLK, CLK FBIN, FBIN FBOUT, FBOUT GND PWRDWN VDDQ Y[0:3] Y[0:3] Pin Number 10 9 6, 7 23, 22 19, 20 1, 5, 14, 15, 28 24 4, 8, 11, 18, 21, 25 3, 12, 17, 26 2, 13, 16, 27 O O I I I O I/O 2.5V analog supply Differential clock input Feedback differential clock input Feedback differential clock output Ground Control input to turn device in the power-down mode 2.5V supply Buffered output copies of input clock, CLK Buffered output copies of input clock, CLK Description Ground for 2.5V analog supply
2
IDTCSPT855 2.5V PLL CLOCK DRIVER
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
FUNCTION TABLE(1)
INPUTS AVDD GND GND X X 2.5V (nom) 2.5V (nom) 2.5V (nom) PWRDWN H H L L H H X CLK L H L H L H <20MHz(2) CLK H L H L H L <20MHz(2) Y L H Z Z L H Z Y H L Z Z H L Z OUTPUTS FBOUT L H Z Z L H Z FBOUT H L Z Z H L Z PLL Bypassed/OFF Bypassed/OFF OFF OFF ON ON OFF
NOTES: 1. H = HIGH Voltage Level L = LOW Voltage Level Z = High-Impedance OFF-State X = Don't Care 2. Typically 10MHz.
RECOMMENDED OPERATING CONDITIONS(1)
Symbol AVDD, VDDQ VIL VIH Supply Voltage Input Voltage LOW Input Voltage HIGH DC Input Signal Voltage(2) VID VO(X) VI(X) IOH IOL SR TA Differential Input Signal Voltage
(3)
Parameter CLK, CLK, FBIN, FBIN PRWDWN CLK, CLK, FBIN, FBIN PRWDWN CLK, FBIN
Min. 2.3 -- - 0.3 VDDQ/2 + 0.18 1.7 - 0.3 0.36 VDDQ/2 - 0.2 VDDQ/2 - 0.2 -- -- 1 Commercial Industrial 0 -40
Typ. -- -- -- -- -- -- -- VDDQ/2 -- -- -- -- -- --
Max. 2.7 VDDQ/2 - 0.18 0.7 -- VDDQ/2 + 0.3 VDDQ VDDQ + 0.6 VDDQ/2 + 0.2 VDDQ/2 + 0.2 - 12 12 4 +70 +85
Unit V V V V V V V mA mA V/ns
Output Differential Cross-Voltage(4) Input Differential Pair Cross-Voltage(4) HIGH-Level Output Current LOW-Level Output Current Input Slew Rate, see figure 8 Operating Free-Air Temperature
C
NOTES: 1. Unused inputs must be held HIGH or LOW to prevent them from floating. 2. DC input signal voltage specifies the allowable DC execution of differential input. 3. Differential input signal voltage specifies the differential voltage | VTR - VCP | required for switching, where VTR is the true input level and VCP is the complementary input level. 4. Differential cross-point voltage is expected to track variations of VDDQ and is the voltage at which the differential signals must be crossing.
3
IDTCSPT855 2.5V PLL CLOCK DRIVER
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified: Commercial: TA = 0C to +70C; Industrial: TA = -40C to +85C
Symbol VIK VOH VOL IOH IOL VOD VOX II IOZ IDD(PD) IDD AIDD CI CO Parameter Input Voltage (All Inputs) HIGH-Level Output Voltage LOW-Level Output Voltage HIGH-Level Output Current LOW-Level Output Current Output Voltage Swing Output Differential Cross Voltage(2) Input Current High-Impedance State Output Current Power-Down Current on VDDQ and AVDD Dynamic Current on VDDQ Supply Current on AVDD Input Capacitance Output Capacitance CL = 14pF CL = 0pF Conditions VDDQ = 2.3V, II = -18mA VDDQ = Min. to Max., IOH = -1mA VDDQ = 2.3V, IOH = -12mA VDDQ = Min. to Max., IOL = 1mA VDDQ = 2.3V, IOL = 12mA VDDQ = 2.3V, VO = 1V VDDQ = 2.3V, VO = 1.2V Differential outputs are terminated with 120 Differential outputs are terminated with 120 VDDQ = 2.7V, VI = 0V to 2.7V VDDQ = 2.7V, VO = VDDQ or GND CLK and CLK = 0MHz, PWRDWN = LOW, of IDD and AIDD fO = 167MHz, Differential outputs terminated with 120 fO = 167MHz, Differential outputs terminated with 120 fO = 167MHz VDDQ = 2.5V, VI = VDDQ or GND VDDQ = 2.5V, VI = VDDQ or GND -- -- -- 2 2.5 150 130 8 2.5 3 180 160 10 3 3.5 mA pF pF mA Min. -- VDDQ - 0.1 1.7 -- -- - 18 26 1.1 VDDQ/2 - 0.2 -- -- -- Typ.(1) -- -- -- -- -- - 32 35 -- VDDQ/2 -- -- 100 Max. - 1.2 -- -- 0.1 0.6 -- -- VDDQ - 0.4 VDDQ/2 + 0.2 10 10 200 mA mA V V A A A V Unit V V
NOTES: 1. All typical values are at respective nominal VDDQ. 2. Differential cross-point voltage is expected to track variation of VDDQ and is the voltage at which the differential signals must be crossing.
TIMING REQUIREMENTS
Symbol fCLK tDC tL tL Parameter Operating Clock Frequency Input Clock Duty Cycle Stabilization Time (PLL Mode)(1) Stabilization Time (Bypass Mode)(2) Min. 60 40 -- -- Max. 180 60 10 30 Unit MHz % s ns
NOTES: 1. Recovery time required when the device goes from power-down mode into bypass mode (test mode with AVDD at GND). 2. Time required for the integrated PLL circuit to obtain phase lock of its feedback signal to its reference signal. For phase lock to be obtained, a fixed-frequency, fixed-phase reference signal must be present at CLK. Until phase lock is obtained, the specifications for propagation delay, skew, and jitter parameters given in the switching characteristics table are not applicable. This parameter does not apply for input modulation under SSC application.
4
IDTCSPT855 2.5V PLL CLOCK DRIVER
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
SWITCHING CHARACTERISTICS
Symbol tPLH(2) tPHL(2) tJIT(PER)(3) tJIT(CC)(3) tJIT(HPER)(3) Description LOW to HIGH Level Propagation Delay Time HIGH to LOW Level Propagation Delay Time Jitter (period), see figure 6 Jitter (cycle-to-cycle), see figure 2 Half-Period Jitter, see figure 7 Test Conditions Test mode, CLK to any output Test mode, CLK to any output 66MHz 100/ 133/ 167/ 180 MHz 66MHz 100/ 133/ 167/ 180 MHz 66MHz 100MHz 133/ 167/ 180 MHz tSLR(O) Output Clock Slew Rate (single-ended), see figure 8 Load: 120 / 14pF Load: 120 / 4pF 66MHz SSC Off tD()(3) Dynamic Phase Offset (includes jitter) see figure 4 SSC On t () tSK(O)(4) tR, tF Static Phase Offset, see figure 3 Output Skew, see figure 5 Output Rise and Fall Times (20% to 80%) Load: 120 / 14pF 100/ 133 MHz 167/ 180 MHz 66MHz 100/ 133 MHz 167/ 180 MHz 66MHz 100/ 133/ 167/ 180 MHz Min. -- -- - 55 - 35 - 60 - 50 - 130 - 90 - 75 1 1 - 180 - 130 - 90 - 230 - 170 - 100 - 150 - 100 -- 650 Typ.(1) 4.5 4.5 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Max. -- -- 55 35 60 50 130 90 75 2 3 180 130 90 230 170 100 150 100 50 900 ps ps ps ps V/ns ps ps Unit ns ns ps
NOTES: 1. All typical values are at respective nominal VDDQ. 2. Refers to transition of non-inverting output. 3. This parameter guaranteed by design but not production tested. 4. All differential output pins are terminated with 120 / 14pF.
5
IDTCSPT855 2.5V PLL CLOCK DRIVER
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
TEST CIRCUIT AND SWITCHING WAVEFORMS
VDD/2 SCOPE Z = 60 C = 14pF VDD/2 VTT Z = 60 C = 14pF VDD/2 CSPT855 VDD/2
NOTE: 1. V(TT) = GND
R = 10
Z = 50 R = 50
R = 10
Z = 50
R = 50 VTT
Figure 1. Output Load Test Circuit
Yx, FBOUT Yx, FBOUT
tcycle n tjit(cc) = tcycle n
tcycle n+1 tcycle n+1
Figure 2. Cycle-to-Cycle jitter
6
IDTCSPT855 2.5V PLL CLOCK DRIVER
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
TEST CIRCUIT AND SWITCHING WAVEFORMS
CLK CLK
FBIN FBIN
t(O)n
t(O)n + 1
t(O)
=
n=N 1 N
(N is a large number of samples)
t(O)n
Figure 3. Static Phase Offset
CLK CLK
FBIN FBIN t(O) tD(O) tD(O) tD(O) t(O) tD(O)
Figure 4. Dynamic Phase Offset
Yx Yx
Yx, FBOUT Yx, FBOUT
tsk(o)
Figure 5. Output Skew 7
IDTCSPT855 2.5V PLL CLOCK DRIVER
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
TEST CIRCUIT AND SWITCHING WAVEFORMS
Yx, FBOUT Yx, FBOUT
tcycle n
Yx, FBOUT Yx, FBOUT 1 fo 1 fo
tjit(per)
=
tcycle n
Figure 6. Period jitter
Yx, FBOUT Yx, FBOUT
thalf period n
Yx, FBOUT Yx, FBOUT 1 fo
thalf period n+1
tjit(hper) = thalf period n
1 2*f o
Figure 7. Half-Period jitter
8
IDTCSPT855 2.5V PLL CLOCK DRIVER
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
TEST CIRCUIT AND SWITCHING WAVEFORMS
80% C lock Inputs and O utputs 20%
80% VID, V O D 20%
tSLRR(I), tSLRR(O)
tSLRF(I), tSLRF(O)
Figure 8. Input and Output Slew Rates
9
IDTCSPT855 2.5V PLL CLOCK DRIVER
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
ORDERING INFORMATION
IDTCSPT XXXXX Device Type X XX Package Process Blank I 0C to +70C (Commercial) -40C to +85C (Industrial)
PG
Thin Shrink Small Outline Package
855
2.5V PLL Clock Driver
CORPORATE HEADQUARTERS 2975 Stender Way Santa Clara, CA 95054
for SALES: 800-345-7015 or 408-727-6116 fax: 408-492-8674 www.idt.com
for Tech Support: logichelp@idt.com (408) 654-6459
10

▲Up To Search▲

Price & Availability of IDTCSPT855

	To Download IDTCSPT855 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .